RFIC-design of 40GHz Multiplier and Buffers

Acreo AB is developing a low-cost radar for automotive applications operating at 77 GHz. Several RF blocks have been designed and tested. For a complete system there is a need to design the remaining IC blocks. This Master Thesis Work is focused on the design of a multiplier and output buffers in a SiGe BiCMOS process. The multiplier block should multiply a 20 GHz input by 2 to get 40 GHz output. Buffer blocks at 40 GHz are required to link the on-chip signal to the off-chip load. Two Master Thesis students are planned to complete the described task. One student should focus on the multiplier block and another student should design the buffers.

Required Background
• Experience with Cadence® ICdesign tool for simulation and layout
• Knowledge in analog RF design
• Ability to work in a team
• Experience with 3D electromagnetic field simulators is an advantage

Task
This Master Thesis will start with literature studies to get a feeling how a radar system works and analyze Design Requirement Specifications for the multiplier and output buffers. The next step is an overview and selection of suitable candidates for the specified block implementation. Then follow schematic simulation and optimization to meet the specified requirements. A complete schematic block should be verified in a radar system test bench simulation. When the schematic design is ready, the corresponding physical layout design has to be done. To verify the designed layout, an extracted schematic will be simulated. Finally, the design has to be documented and presented to Acreo AB. The Master Thesis students are expected to participate and contribute in design and test reports according to Acreo quality requirements. The described tasks for each student are summarized below.
• Brainstorming and literature studies
• Schematic simulation
• System simulation
• Physical layout design
• Design documentation
• Presentation